Pascal Vivet

He received his PhD from Grenoble Polytechnical Institute in 2001, designing an asynchronous microprocessor. After 4 years within STMicroelectronics, he joined CEA-Leti in 2003 in the digital design lab. His research interests covers wide aspects of circuit and system level design, ranging from system integration, multi-core architecture, Network-on-Chip, Energy efficient design, CAD design aspects, and in strong links with advanced technologies such as 3D integration, Non-Volatile-Memories, photonics.

He was project leader on 3D circuit design and integration from 2011 to 2020 ; co-director of the IRT Smart Imager program from 2021 to 2023 ; Scientific Director of the Digital Systems and Integrated Circuits Division in CEA-LIST from 2020 to 2025 ; and more recently He was Manager of the 3D Heterogeneous Integration Laboratory and team, providing optimized 3D integration, packaging and chiplet strategies for demanding applications, from 2025 to 2026.

He has participated actively to the TPC of various conferences such as DATE, DAC, ASYNC, NOCS, 3DIC, ISLPED, ESSERC. He served as a member of the organizing committee of the 3D workshops series in DATE from 2013 to today. He has authored and co-authored more than 120 papers and holds several patents in the field of digital design. He is member of IEEE, and CEA Fellow.